Chasen Peters: SRAM Memory Compiler

Student's Name: 
Chasen Peters
Advisor's Name: 
Matthew Guthaus
Home University: 
University of California Santa Cruz
SRAM Memory Compiler
Chasen Peters, Sekjoong Kim, Marcelo Siero, Matthew Guthaus
Computer Engineering, University of California, Santa Cruz
The VLSI-DA group at the University of California, Santa Cruz has been an excellent opportunity. 
This lab focuses on finding solutions to challenging VLSI design problems by designing tools to automate 
the process. Not only does this require a fundamental command of VLSI design but a sense of engineering 
creativity.  I have enjoyed my work within this lab because I can take my interest in hardware design 
and transition it into learning how to design software that will design hardware for me. 
I found my niche within this group after taking an undergraduate course in logic design with Prof. Matthew Guthaus. 
After the course ended I continued on as a lab tutor for Prof. Guthaus. Due to my performance as a tutor and his 
course, I was offered a seat in Prof. Guthaus’s graduate VLSI course. My project for this course was to 
design a software package that would allow the memory compiler his lab was working on to layout a special 
SRAM memory array that would work on low voltages. After the course ended I continued with this 
research on the side and was eventually given a spot within the SURF-IT program here and UCSC. 
This program provided me with the funding necessary to continue working on this project full time over the summer. 
The main drive behind this project is to design an easy to use, open source, CAD tool capable 
of providing multiple levels of abstraction for system designers and memory researchers alike. Most
tools within the industry require expensive licenses and are unlikely to give the designer access to 
the lower level details of a particular memory that is being used. With this compiler it is possible to 
have a community maintained tool that is readily available to those who wish to use it. This tool will offer
fast front end testing for those users who wish to stay clear of layout details, as well as back- annotated 
simulation with the extracted parasitic. At the moment the compiler is configured to layout an array using 
the start 6 transistor SRAM, but it can easily be configured to layout 8 transistor, 10 transistor, or any other 
desired bit cell. The compiler will also offer options such as reliability through redundancy and automated 
timing analysis. The end product is a highly tuned memory model that will reflect the behavior of the fabricated memory.