Kathryn Dobbins: Reducing Power Consumption in Clock Grids

Kathryn Dobbins is majoring in Computer Engineering at Michigan Technological University.  Kathryn worked in the VLSI Design Automation Lab at UCSC through the SURF-IT program the summer of 2011 with Matthew Guthaus as her advisor.  

The UCSC VLSI Design Lab focuses it's research on reliability, variability, and low-power, one aspect of this being clocks.  One way to help insure that the clock signal reaches all the components at approximately the same time is through the use of a grid of wires.  This grid of wires helps stabilize the grid, which is beneficial due to the variability of wires and buffers.  However, this grid of wires must be driven by large buffers and, therefore, uses significant power.  One way to reduce the power consumption of the grid is to remove wires that do not significantly help performance.  Kathryn analyzed various possible ways of determining which wires to remove.  Based off of the information she gathered, she created a fast algorithm that uses current flow as a metric to determine which grid wires should be removed from the grid.