Edward Sullivan: Algorithm For Cross-Link Insertion To Improve Efficiency of Local Resonant Clock Trees

In the autumn of 2011, Edward Sullivan will enter his third year studying Computer Engineering at Clemson University in South Carolina. He spent the summer of 2011 performing research with Professor Matthew Guthaus's VLSI Design and Automation Group at UC Santa Cruz. There he explored techniques to improve efficiency in the clock networks of chips. Clocks account for about 40% of chip power requirements and much research focuses on reducing these power needs so as to conserve electricity, allow clocks to run faster, and prevent heating problems.

Jas Condely, a PhD student in Edward's lab, had previously developed a method to insert inductor-capacitor tanks into local clock trees and thereby use resonance to cut tree power needs by an average of 75%. However, due to the high resistivity of wires in clock trees, these resonant tanks are restricted to small tree sizes. The goal of Edward's research was to  further reduce power consumption and to increase local resonant tree sizes by selectively widening wires and inserting cross-links between branches of local trees while maintaining a low total capacitance. The challenge of the project was in balancing the benefits of reduced tree resistance with the negative effects of a greater  tree capacitance when applying these methods.

Edward successfully developed a wire-width adjustment algorithm that may reduce resonant tree power needs by 10 % in Spice simulations. He discovered that adjusting wire-width is a more effective power-reduction technique than adding cross-links is. The experience has solidified Edward's interest in research and his desire to pursue a PhD.