Ryan Conway: Standing Wave Oscillators for Global Clock Distribution

The clock signal of modern computer processors consumes a large portion of overall chip power. By reducing clock power consumption, we can prolong mobile device battery life and tackle the larger, increasingly pervasive issue of overall energy conservation. This approach explores using signal reflections to produce a 10GHz standing wave oscillator (SWO) for global clock distribution. By choosing precise wire geometries, we can use such reflections constructively, creating a sink voltage notably larger than the source voltage.

Wires are modeled as lossy, distributed, uniform RLC transmission lines. Branch impedances are matched such that maximum power is transferred. Transmission line parameters are based off of ASU's Predictive Technology Model. Tests run using the HSPICE circuit simulator reveal power savings of 73% for a uniform global clock network. Ongoing work involves adjusting line capacitances to manipulate phase shift, as well as exploring realistic nonuniform sink distributions.

Ryan Conway will be a fourth-year computer engineering student at UC Santa Cruz in fall of 2011. He took a logic design course and a graduate VLSI course with Professor Matthew Guthaus in the 2009-2010 academic year, and over the summer worked in Prof. Guthaus' VLSI design automation lab.