Benjamin LaCara: Physical Design of Rachael SPARC

The Very Large Scale Integration Design Automation (VLSI-DA) group at UCSC has a strong focus on physical circuit design, high-performance resonant clock systhesis and large-scale circuit optimization. My work in this group has been to create both 90nm and 45nm physical implementations of a 32-bit, open-source microprocessor, called Rachael SPARC. This work is jumping off from the Micro Architecture Lab at Santa Cruz's (MASC) progress on developing Rachael. The physical implementation is a test vehicle for high-performance resonant clock synthesis using on-chip inductors that recycle the energy of the clock network. Our physical implementation is created using a commercial ASIC design flow with Synopsys Design Compiler and Cadence First Encounter. By interfacing to these tools through the Design Exchange Format (DEF), our resonant clock synthesis tool adds resonant clocks to the prototype microprocessor.

Benjamin LaCara is going into his 5th year as a computer engineering student at UCSC in the Fall of 2011. He will be continuing his work from SURF-IT in the VLSI-DA group and related course both led by Prof. Matthew Guthaus.