Miguel Salcedo: FPGA Overclocking: Developing a platform to model IC variability

Miguel A Salcedo is an undergraduate electrical engineer at San Jose State University. Miguel spent the summer under the supervision of Professor Jose Renau at the Computer Science lab. During his stay, Miguel worked in the development of a platform to model IC's variability. The main goal of his research project was to construct a model to map IC’s variability.

Variability is one of the main limiters in VLSI scaling specially when going beyond the 65nm. Finding the chips variability would help organize and develop in future research a dynamic processor unit, in order to improve the usage of the IC’s in silicon.

In order to map variability, he came up with a set of multipliers that are linked together throughout the target IC chip. The project consisted of running the multipliers at high frequencies and till they provided erroneous data, which was used to map (estimate) the possible location that variability occurs the most in the silicon chip. As variability increases, the performance of the IC decreases exponential.